Building Online Power Models from Real Data

MICRO-48 Tutorial
December 5, 2015
Waikiki, Hawaii

Refer to our new website (http://www.powmon.ecs.soton.ac.uk/powermodeling/) for the latest news, publications and software tools.

In this hands-on, interactive tutorial, you will learn how to efficiently build accurate, run-time power models using real hardware platforms using a specially built software tool. Starting from the basics of how power is consumed in a modern system-on-chip through static and dynamic power in the underlying transistors, we show how activity, voltage and frequency affect the power consumption.

We will then let you play with a board that we have prepared to be easy to work with and walk you through practicalities, such as workload selection and how to get activity information. With the basics from the first section, you will be able to build your own power model for the test platform quickly.

Once you have built a simple power model for your test board, we will introduce a surprise workload which we will then use to put the generated power models through a real-life test: running a workload that was not anticipated at model construction time. We will even give out prizes for the ones closest to the real power consumption.

Content

  • Introduction to Power Modelling with performance counters (PMCs) and power measurements
  • Interactive session running experiments to gather required data
  • Introduction to regression analysis
  • Interactive session analysing gathered data and selecting suitable performance counters
  • Presentation on fun competition and a surprise workload
  • Interactive session where the participants predict the power of the surprise workload
  • Announcing the winner of the competition and giving of prizes
  • Closing remarks

Schedule

Saturday 5th December, Afternoon, Session D, Room TBA

Time Title Presenter
13:00 Welcome and introduction
13:15 Motivation for top-down power models
13:30 Introduction to our modelling workflow and software
14:00 Hands-on!
15:00 Break
15:30 Hands-on (part II)
16:00 Deeper look at the methodology
16:45 Conclusion and Compition Results

Registration and Logistics

Registration will be through the MICRO-48 Conference Website.

Participants will not require any specialist knowledge, general programming knowledge is of an advantage, however. Experimentation boards and prizes are provided (with kind support from ARM Research), so attendees do not need to bring any additional material.

Why (Top-Down) Power Models?

Power models are a key ingredient in both analysing future energy-efficient computer systems, for example in design-space exploration, and also when optimising existing system stacks. Particularly in mobile devices, energy efficiency is a vital factor; understanding how, where and why power is used at run-time can enable significant platform optimisations (dynamic voltage and frequency scaling; thermal boosting; intelligent distribution of available TDP between CPU and GPU cores; scheduling tasks in heterogeneous systems, such as ARM's big.LITTLE™ architectures). In research and design-space exploration, power models built and validated on real hardware with measured power data are extremely valuable as their accuracy is known and trusted, as opposed to models based on theoretical synthesis data deriving power consumption from the bottom up.

Top-down power models aggregate several high-level activity vectors which can be observed at runtime through performance monitoring counters (PMCs), and relate them to measured power consumption numbers. Despite the conceptual simplicity of the approach, several challenges need to be overcome leading to a significant lack of published mobile-based PMC-models. In our tutorial, we address the existing key issues with empirical run-time power modelling:

  • Finding a suitable, modern platform where power data can be extracted is difficult;
  • Performance counter (PMCs) are difficult or impossible to obtain on many platforms;
  • The technical 'hands-on' work is very time-consuming;
  • There is a lack of published model coefficients;
  • There is a shortage of meticulous PMC event selection methodologies;
  • Existing work generally does not give enough statistical information about the produced models and the validation process;
  • Many important modelling problems that PMC models are susceptible to, such as multicollinearity and heteroscedasticity, are not considered.

We address these issues in the proposed interactive tutorial by providing a tried-and-tested hardware platform with a custom-built OS image and software that provides power and PMC data and a full experimental framework for repeatable experiments. We also provide custom-built analysis, model building and model validation scripts that automate the workflow and provide features to address the problems specific to PMC-based model building.

We will share our experience and expertise in power modelling and guide participants in building performance counter-based run-time power models in the tutorial itself. In this tutorial we will focus on the power consumption of different CPU cores, caches, and interconnects; the methodolgy will, however, easily translate to other components, such as memory and GPUs.

In summary, the provided development framework allows experimental research be completed including graphs and output statistics by the end of the tutorial. Previously, this work could have taken many weeks to complete. We hope that by showing how to build high-quality power models and by providing hardware and software tools, we will greatly encourage and strengthen research in this area.

Organisers and Contact

Matt Walker

Matt Walker is a PhD student at the University of Southampton, UK, working on power estimation in mobile platforms. He recently completed an internship in ARM, Cambridge, UK, where he worked on run-time model building methodologies and developed software to automate the process.
Email: mw9g09@ecs.soton.ac.uk

Vasileios Spiliopoulos Photo

Vasileios Spiliopoulos is a PhD student at Uppsala University, Sweden, working on energy-efficient hardware architectures and the use of dynamic voltage and frequency scaling (DVFS). In previous internships at ARM he has extended the gem5 simulator with support for DVFS and power state modelling.
Email: vasileios.spiliopoulos@it.uu.se

Stephan Diestelhorst Photo

Stephan Diestelhorst is a Staff Research Engineer at ARM, Cambridge, UK. He leads a group that predicts and improves power consumption of future SoCs using the gem5 simulator and native hardware. Before joining ARM in 2013, Stephan worked at Advanced Micro Devices, in Dresden, Germany as a researcher in the Operating Systems Research Center.
Email: stephan.diestelhorst@arm.com